Specifically, IBM says it will "open" the instruction set architecture (ISA) of its OpenPower family of CPUs. Given that the ISA is, and for years has been, available online to read, by "opening" the architecture, Big Blue means it is licensing its technology to everyone to use, royalty free. This will allow people to implement and manufacture their own processors capable of running software built for OpenPower.
Big Blue Open Sources Power Chip Instruction Set
RISC-V is an open-source, royalty free processor ISA: people can implement their own RISC-V-compatible processors, and choose to keep the designs closed or open. Quite a few cores end up open, encouraging more to participate in the ecosystem, customizing and improving designs, and contributing back. SiFive will let you configure and order a RISC-V system-on-chip from your browser. Big names, such as Google, Qualcomm, Nvidia, Samsung, Western Digital, are backing it. The platform has an increasing amount of buzz around it. Google was also a big backer of OpenPower when it launched, we note.
RISC-V implementations and specifications seem to be quietly flying under the radar into China from the US, while the likes of Huawei are being used as gigantic bargaining chips. Perhaps IBM wants to glide in behind RISC-V, open up its ISA as a royalty-free open specification, and drop its documentation into as many hands as it can, in any country it can legally deal with, without any politics getting in the way.
AWS Graviton processors feature key capabilities that enable you to run cloud native applications securely, and at scale. AWS Graviton3 processors feature always-on memory encryption, dedicated caches for every vCPU, and support for pointer authentication. EC2 instances powered by AWS Graviton processors are built on the AWS Nitro System that features the AWS Nitro security chip with dedicated hardware and software for security functions, and support for encrypted Amazon Elastic Block Store (EBS) volumes by default.
There has never been a free (open-source) instruction set for computer chips before. Big companies had to pay for the instructions on the chip. Now huge orders don't need to pay royalties to the chip manufacturers. This saves millions of dollars and allows for more free trade.
The adoption of RISC-V, a free and open-source computer instruction set architecture first introduced in 2010, is taking off like a rocket. And much of the fuel for this rocket is coming from demand for AI and machine learning. According to the research firm Semico, the number of chips that include at least some RISC-V technology will grow 73.6 percent per year to 2027, when there will be some 25 billion AI chips produced, accounting for US $291 billion in revenue.
Future RISC-V processors will be able to tackle machine-learning-related operations using an open-source set of instructions agreed upon by the community. RISC-V International, the body that governs the codification of the core instruction set architecture and new extensions, ratified a set of just over 100 vector instructions in December 2021.
In 2018, the open source instruction set architecture RISC-V emerged as a force to reckon with in the hard-to-crack silicon market. The ball got started early last year, when SiFive, a Silicon Valley startup built around the open silicon design, quickly sold out on a limited run of a single-board computer for RISC-V developers, HiFive Unleased, that it offered on a crowdfunding site for the premium price of $999 apiece, resulting in gross sales of $143,700.
The reduced instruction set architecture (pronounced "risk-five") is becoming increasingly attractive to hardware manufacturers, especially those building embedded IoT or edge devices. Like Arm processors, the architecture only requires a small amount of power when compared to x86 devices from Intel or AMD, with some benchmarks indicating it's even more energy efficient than Arm, which has become the gold standard for battery-operated devices.
The major advantage of the ISA (Instruction Set Architecture) over Arm, however, is that RISC-V is open source. OEMs can use the specification to design and manufacture chips paying little to no royalties, which is a large part of the price of bringing an Arm chip to market. Some users also find further advantage in RISC-V's "permissive" BSD licensing, which means customized RISC-V chips can be made proprietary for IP protection, if desired.
Other core releases have been in the news this year. Most notably, Western Digital's open source release in January of the 32-bit SweRV Core EH1 developed for use in its upcoming products. According to Western Digital, the core is designed for embedded devices running data-intensive applications, such as storage controllers, industrial IoT devices, real-time analytics in surveillance systems, and the like. Typical for RISC-V, the processor sips power and clocks in at up to 1.8Ghz while running on a 28nm CMOS battery.
RISC architecture requires more clock cycles to complete the same instruction as CISC but can do so more efficiently, making it ideal for mobile applications. However, x86/x64 remains the dominant architecture in heavy processing markets. But ARM may face serious competition from a new processor architecture, RISC-V, which is open-source, customisable and does not require any royalties or licenses.
RISC-V is an open standard instruction set architecture (ISA) based on Reduced Instruction Set Computer (RISC) principles. RISC-V uses a smaller and simpler instruction set compared to Complex Instruction Set Computer (CISC) architectures, such as x86 and ARM. This allows for more efficient and faster processing of instructions and smaller and more power-efficient designs.
On the other hand, RISC-V is open-source and does not require royalties or licenses, allowing for greater flexibility and customisation. Designers can experiment and develop RISC-V systems for free and can even modify the instruction set architecture to match specific application requirements. However, the lack of the proprietary nature of RISC-V also means that there is little to no support for hardware design. ARM provides teams of engineers developing hardware systems that make it easy for designers to incorporate ARM CPUs. This can be a significant advantage for designers unfamiliar with developing hardware.
RISC-V processors, which are based on the Reduced Instruction Set Computer (RISC) architecture, generally have a higher instruction-per-cycle (IPC) performance compared to ARM processors, which are based on the Complex Instruction Set Computer (CISC) architecture. This is because RISC-V processors have a simpler instruction set architecture, allowing them to execute instructions faster and more efficiently. Because RISC-V processors have fewer instructions to execute, they require fewer cycles to complete a task, resulting in a higher IPC performance. Additionally, RISC-V processors have a simpler pipeline, which allows them to execute instructions in parallel, further increasing their performance. In contrast, ARM processors have a more complex instruction set and pipeline, which can lead to increased power consumption and lower performance.
The team says their motivation and goals are driven by the desire to create a small, area-efficient design with custom programmability and extensibility. It should offer low-cost IP ownership and development, and not compete with commercial offerings. It can be implemented in FPGA and ASIC targets and will be free and open source. The initial design will be targeted to low-power microcontrollers. It will be Khronos Vulkan-compliant, and over time support other APIs (OpenGL, DirectX and others).
This is a very early spec, still in development and subject to change based on stakeholder and industry input. The team will establish a discussion forum. An immediate goal isbuilding a sample implementation with instruction set simulator, an FPGA implementation using open-source IP and custom IP designed as open-source project. Demos and benchmarks are being designed. Developers interested in participating should contract Atif Zafar.
Many of the differences between RISC-V, ARM, and x86 microprocessors are subtle and relate to how memory is addressed, branches are executed, exceptions are handled, and so on. This article will consider higher-level differences and will briefly compare reduced instruction set computing (RISC) and complex instruction set computing (CISC), consider the impact those differences have on the tradeoff between power consumption and computing performance, look at how security and predicated execution are handled, how virtualization is implemented, and end with an overview of applications suitability for RISC-V, ARM, and x86 devices.
From this equation, there are two ways to improve performance, minimize the number of instructions per program or reduce the number of cycles per instruction. In general, the RISC approach is more successful in reducing overall power consumption, sometimes at the expense of lower performance. However, the lines of difference are narrowing. ARM has added more complex instructions to increase processor performance (at the expense of higher power consumption). Intel breaks down some of its opcodes into micro-ops that are RISC-like to achieve lower power consumption.
The RISC-V H (hypervisor) extension v0.6.1 introduces a full duplicate of the CPU state: one copy for the guest and one copy for the host (similar to Intel VT-x). RISC-V supports the virtualization of CPUs by making sensitive registers and instructions privileged to host mode. As seen from the pre-release version number, RISC-V virtualization is a work in process. The first public implementation and evaluation was recently published of the latest version of the RISC-V hypervisor extension in a Rocket chip core for use in embedded systems.
For chip designers, RISC processors simplify the design and deployment process and provide a lower per-chip cost due to the smaller components required. Because of the reduced instruction set and simple decoding logic, less chip space is used, fewer transistors are required, and more general-purpose registers can fit into the central processing unit. 2ff7e9595c
Comments